It is well known that feature sizes of advanced integrated circuits (ICs) are shrinking with each new fabrication technology node, requiring photolithographic patterns with increasingly higher resolution to form the IC features. The resolution of a photolithographic pattern is a function of the wavelength of the light and the optical lens in the photolithographic equipment used to expose photoresist to form the pattern. New illumination sources with reduced wavelengths have been introduced to produce photolithographic patterns with higher resolution, but the reduction trend in wavelength has not kept up with the shrink rate of IC features. Similarly, improvements in optical lenses in photolithographic equipment have not matched IC feature shrink rates. To maintain photolithographic pattern integrity, the reticle pattern is manipulated from the IC layout pattern, in a process commonly known as optical proximity correction (OPC), to account for optical interference effects during printing the photolithographic patterns. OPC schemes typically use one-dimensional pattern transfer functions and empirically measured pattern contours of selected structure-specific patterns. Generating reticle patterns for ICs using such OPC schemes is problematic, because IC layouts include complex features which are not adequately addressed by one-dimensional models and which do not match the available structure-specific features.